Many discrete metal oxide semiconductor field effect transistor (MOSFET) device layouts include a gate pad in a die with dimensions large enough to accommodate a bond wire or other attachment. Because of this size requirement, the gate pad can take up a large portion (e.g., 50%, etc.) of a small die. Further, because in many examples there is no active area under the gate pad, the required gate pad size can limit the active area in the semiconductor device.
FIG. 1 illustrates generally an example of a portion of a semiconductor device 100 including a source contact 102, a gate dielectric 103, a gate bus 104, a gate structure 105, a second dielectric 106, and a substrate 113. In certain examples, the gate structure 105 can include a gate pad, a gate runner, or one or more other gate contacts or gate bus structures, and can be sized to provide an adequate bonding area. In certain examples, the substrate can be isolated from the gate bus by a thin dielectric material (not shown), such as a gate oxide.
In this example, the source contact 102 is isolated from the gate structure 105 by a gap 107 configured to maintain a minimum distance, and provide proper isolation, between the gate structure 105 and the source contact 102, and the source contact 102 is isolated from the gate bus 104 by the second dielectric 106. In various examples, the inactive area of a particular semiconductor device can vary depending on the processing and design parameters used to make and operate the device. In the example of FIG. 1, the edge of the source contact 102 roughly defines an inactive area 111 below the gate bus 104 that limits an active area 108 of the semiconductor device 100. In general, an inactive area of a device, such as a power FET device, is area that cannot be used to create a functional channel to conduct current.
In an example, the active area 108 of the die can include one or more trenches forming an active trench array. In certain examples, one or more gate electrodes disposed in the active trench array can form a portion of a source region of the semiconductor device 100, a portion of which can be laterally offset from the gate structure 105. In certain examples, a lower surface of the substrate 113, substantially opposite a top working surface of the semiconductor device 100, can include a drain region of the semiconductor device 100. In certain examples, the inactive area 111 below the gate structure 105 can have a width greater than about 55 um.